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W255
200-MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS
Features
* One input to 24-output buffer/driver * Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS * One additional output for feedback * SMBus interface for individual output control * Low skew outputs (< 100 ps) * Supports 266-, 333-, and 400-MHz DDR SDRAM * Dedicated pin for power management support * Space-saving 48-pin SSOP package
Functional Description
The W255 is a 3.3V/2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 24 outputs. Designers can configure these outputs to support four unbuffered DDR DIMMS or to support three unbuffered standard SDRAM DIMMs and two DDR DIMMS. The W255 can be used in conjunction with the W250 or similar clock synthesizer for the VIA Pro 266 chipset. The W255 also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull up).
Block Diagram
FBOUT
BUF_IN DDR0T_SDRAM10 DDR0C_SDRAM11 DDR1T_SDRAM0 DDR1C_SDRAM1
Pin Configuration
SSOP Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
SDATA SMBus Decoding SCLOCK
R_DWN#
Power Down Control
FBOUT VDD3.3_2.5 GND DDR2T_SDRAM2 DDR0T_SDRAM10 DDR2C_SDRAM3 DDR0C_SDRAM11 DDR3T_SDRAM4 DRR1T_SDRAM0 DDR3C_SDRAM5 DDR1C_SDRAM1 VDD3.3_2.5 DDR4T_SDRAM6 GND DDR4C_SDRAM7 DDR2T_SDRAM2 DDR5T_SDRAM8 DDR2C_SDRAM3 DDR5C_SDRAM9 VDD3.3_2.5 BUF_IN DDR6T GND DDR6C DDR3T_SDRAM4 DDR7T DDR3C_SDRAM5 DDR7C VDD3.3_2.5 DDR8T GND DDR8C DDR4T_SDRAM6 DDR9T DDR4C_SDRAM7 DDR5T_SDRAM8 DDR9C DDR5C_SDRAM9 DDR10T VDD3.3_2.5 SDATA DDR10C DDR11T DDR11C
SEL_DDR* VDD2.5 GND DDR11T DDR11C DDR10T DDR10C VDD2.5 GND DDR9T DDR9C VDD2.5 PWR_DWN#* GND DDR8T DDR8C VDD2.5 GND DDR7T DDR7C DDR6T DDR6C GND SCLK
SEL_DDR
Note: 1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
Cypress Semiconductor Corporation Document #: 38-07255 Rev. *C
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 14, 2002
W255
Pin Summary
Pin Name SEL_DDR Pins 48 Pin Description Input to configure for DDR-ONLY mode or STANDARD SDRAM mode. 1 = DDR-ONLY mode. 0 = STANDARD SDRAM mode. When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, pin 4, 5, 6, 7, 10, 11,15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as DDR outputs. Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode. When SEL_DDR is pulled LOW or configured for STANDARD SDRAM output, pin 4, 5, 6, 7, 10, 11, 15, 16, 19 and 20, 21, 22 will be configured as STANDARD SDRAM outputs.Pin 27, 28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as DDR outputs. Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM mode. SCLK SDATA BUF_IN FBOUT PWR_DWN# DDR[6:11]T DDR[6:11]C DDR[0:5]T_SDRAM [10,0,2,4,6,8] 25 24 13 1 36 28, 30, 34, 39, 43, 45 27, 29, 33, 38, 42, 44 4, 6, 10, 15, 19, 21 SMBus clock input SMBus data input Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V input for STANDARD SDRAM mode. Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V. Active LOW input to enable power-down mode; all outputs will be pulled LOW. Clock outputs. These outputs provide copies of BUF_IN. Clock outputs. These outputs provide complementary copies of BUF_IN. Clock outputs. These outputs provide copies of BUF_IN. Voltage swing depends on VDD3.3_2.5 power supply. Clock outputs. These outputs provide complementary copies of BUF_IN when SEL_DDR is active. These outputs provide copies of BUF_IN when SEL_DDR is inactive. Voltage swing depends on VDD3.3_2.5 power supply. Connect to 2.5V power supply when W255 is configured for DDR-ONLY mode. Connect to 3.3V power supply, when W255 is configured for standard SDRAM mode. 2.5V voltage supply
DDR[0:5]C_SDRAM 5, 7, 11, 16, 20, 22 [11,1,3,5,7,9]
VDD3.3_2.5
2, 8, 12, 17, 23
VDD2.5 GND
32, 37, 41, 47
3, 9, 14, 18, 26, 31, 35, 40, 46 Ground
Document #: 38-07255 Rev. *C
Page 2 of 10
W255
Serial Configuration Map
* The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits should be programmed to "0." * SMBus Address for the W255 is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ---Bit 2 Bit 1 Bit 0 10, 11 6, 7 4, 5
Byte 7: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Pin # 30, 29 28, 27 21, 22 19, 20 15,16 Description DDR7T, DDR7C DDR6T, DDR6C DDR5T_SDRAM8, DDR5C_SDRAM9 DDR4T_SDRAM6, DDR4C_SDRAM7 DDR3T_SDRAM4, DDR3C_SDRAM5 DDR2T_SDRAM2, DDR2C_SDRAM3 DDR1T_SDRAM0, DDR1C_SDRAM1 DDR0T_SDRAM10, DDR0C_SDRAM11 1 1 1 1 1 1 1 1 Default
Byte 6: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description Reserved, drive to 0 Reserved, drive to 0 Reserved, drive to 0 FBOUT DDR11T, DDR11C Default 0 0 0 1 1 1 1 1 Bit 7 - Bit 6 - Bit 5 - Bit 4 1 Bit 3 45,44
Bit 2 43, 42 DDR10T, DDR10C Bit 1 39, 38 DDR9T, DDR9C Bit 0 34, 33 DDR8T, DDR8C
Document #: 38-07255 Rev. *C
Page 3 of 10
W255
Maximum Ratings
Supply Voltage to Ground Potential ..................-0.5 to +7.0V DC Input Voltage (except BUF_IN) ............ -0.5V to VDD+0.5 Storage Temperature.................................. -65C to +150C Static Discharge Voltage .......................................... > 2000V (per MIL-STD-883, Method 3015)
Operating Conditions [2]
Parameter VDD3.3 VDD2.5 TA COUT CIN Supply Voltage Supply Voltage Operating Temperature (Ambient Temperature) Output Capacitance Input Capacitance Description Min. 3.135 2.375 0 6 5 Typ. Max. 3.465 2.625 70 Unit V V C pF pF
Electrical Characteristics Over the Operating Range
Parameter VIL VIH IIL IIH IOH IOL VOL VOH IDD IDD IDDS VOUT VOC INDC Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output HIGH Current Output LOW Current Output LOW Voltage[3] Output HIGH Voltage Supply Current[3] (DDR-only mode) Supply Current (DDR-only mode) Supply Current Output Voltage Swing Output Crossing Voltage Input Clock Duty Cycle
[4] [3]
Test Conditions For all pins except SMBus
Min. 2.0
Typ.
Max. 0.8 50 50
Unit V V A A mA mA
VIN = 0V VIN = VDD VDD = 2.375V VOUT = 1V VDD = 2.375V VOUT = 1.2V IOL = 12 mA, VDD = 2.375V IOH = -12 mA, VDD = 2.375V Unloaded outputs, 133 MHz Loaded outputs, 133 MHz PWR_DWN# = 0 See test circuity (refer to Figure 1) 0.7 (VDD/2) -0.1 48 VDD/2 1.7 -18 26 -32 35
0.6 400 500 100 VDD +0.6 (VDD/2) +0.1 52
V V mA mA A V V %
Switching Characteristics
Parameter - - t3 t4 t3d Duty Cycle Name Operating Frequency
[3, 5]
Test Conditions Measured at 1.4V for 3.3V outputs Measured at VDD/2 for 2.5V outputs Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V Measured between 20% to 80% of output (refer to Figure 1)
[3]
Min. 66 INDC -5% 1.0 1.0 0.5
Typ.
Max. 200 INDC +5% 2.75 2.75 1.50
Unit MHz % V/ns V/ns V/ns
= t2 / t1
SDRAM Rising Edge Rate[3] SDRAM Falling Edge Rate DDR Rising Edge Rate[3]
Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Document #: 38-07255 Rev. *C
Page 4 of 10
W255
Switching Characteristics (continued)[4]
Parameter t4d t5 t6 t7 t8 Name DDR Falling Edge Rate[3] Test Conditions Measured between 20% to 80% of output (refer to Figure 1) All outputs equally loaded Input edge greater than 1 V/ns Input edge greater than 1 V/ns 5 5 Min. 0.5 Typ. Max. 1.50 100 150 10 10 Unit V/ns ps ps ns ns
Output to Output Skew for DDR[3] All outputs equally loaded Output to Output Skew for SDRAM[3] SDRAM Buffer LH Prop. Delay[3] SDRAM Buffer HL Prop. Delay[3]
Switching Waveforms
Duty Cycle Timing
t1 t2
All Outputs Rise/Fall Time
2.4V 0.4V t3 2.4V 0.4V t4 3.3V 0V
OUTPUT
Output-Output Skew
OUTPUT
OUTPUT t5
SDRAM Buffer HH and LL Propagation Delay 1.5V
INPUT
OUTPUT t6
1.5V
t7
Document #: 38-07255 Rev. *C
Page 5 of 10
W255
Figure 1 shows the differential clock directly terminated by a 120 resistor. VCC VCC
Device Under Test
Out
) )
60W
VTR RT =120
Out
60W VCP
Receiver
Figure 1. Differential Signal Using Direct Termination Resistor
Ordering Information
Ordering Code W255H W255HT 48-pin SSOP 48-pin SSOP-Tape and Reel Option Package Type Operating Range Commercial Commercial
Document #: 38-07255 Rev. *C
Page 6 of 10
W255
Layout Example for DDR 2.5V Only
FB
VDDQ2
0.005 mF 10 mF
C4 G G
C3
G
G
G
G
G
1G 2V 3G 4 5 6 7G 8V 9G 10 11 G 12 V G 13 14 15 16 G 17 V 18 G 19 20 21 22 G 23 V 24 G
G
48 47 G 46 45 44 43 G 42 V 41 G 40 39 G 38 V 37 G 36 G 35 34 G 33 V 32 G 31 30 29 28 27 G 26 25
V
G
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) or TDK ACB 2012L-120 Ceramic Caps C3 = 10-22 F G = VIA to GND plane layer C4 = 0.005 F V = VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 F ceramic
W255
G
G
Document #: 38-07255 Rev. *C
Page 7 of 10
W255
Layout Example SDRAM (Mixed Voltage)
FB
VDDQ3
FB
VDDQ2
10 mF 10 mF
C4
0.005 mF
C3 G
C1 G
0.005 mf
C2 G
G
G
G
G
G
G
1 2V G 3 4 5 6 7G 8V 9 10 11 G 12V G 13 14 G 15 16 G 17V 18 G 19 20 21 22 23V 24 G
G
48 47 46 45 44 43 G 42 V 41 G 40 39 G 38 V 37 G 36 G 35 34 G 33 V 32 G 31 30 29 28 27 G 26 25
G V
G
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) or TDK ACB 2012L-120 Ceramic Caps C1 and C3 = 10-22 FC2 & C4 = 0.005 F C6 = 0.1 F G = VIA to GND plane layer V = VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 F ceramic
W255
G
G
Document #: 38-07255 Rev. *C
Page 8 of 10
W255
Package Diagram
48-lead Shrunk Small Outline Package O48
51-85061-*C
VIA is a trademark of VIA Technologies, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07255 Rev. *C
Page 9 of 10
(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W255
Document Title: W255 200MHz 24 Output Buffer for 4 DDR or 3 SDRAM DIMMs Document Number: 38-07255 REV. ** *A *B *C ECN NO. 110520 112154 114554 122857 Issue Date 12/04/01 03/01/02 05/07/02 12/14/02 Orig. of Change SZV IKA INA RBI Description of Change Change from Spec number: 38-01082 to 38-07255 Added 333 MHz for DDR SDRAM Added 400 MHz for DDR SDRAM Power up requirements added to Operating Conditions Information
Document #: 38-07255 Rev. *C
Page 10 of 10

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